Computers have been designed with architectures which permit a central processor to respond to an initial set of instructions, called BIOS, followed by instructions from an operating program (operating system software), followed by further programming information embodied by the particular program being run. Various forms of memory are addressed through this architecture. DOS-compatible computers (compatible with MS DOS software, from Microsoft Corporation of Redmond, Washington) have such an architecture. (These computers are also generally operable with other operating systems, such as OS2, UNIX, etc.)
The industry has flourished by using standardized operating programs in order to define the operation of a computer. The standard operating program permits computers from different manufacturers to behave similarly, a fact that is not lost to software developers, who design their programs to operate from the operating system ("DOS") instead of directly from the computer's BIOS. These circumstances provide what is often referred to as DOS compatible computers. These are colloquially referred to as IBM compatible computers, even though specific architectures of the computers differ.
In most computers, the CPU includes system base memory, and read only memory associated with a basic input/output system (BIOS). "BIOS" is an acronym for basic input/output system. It is a set of programs that reside in non-volatile ROM memory. The BIOS includes the power-on diagnostics, a boot-up program, and device drivers for the keyboard, disk, display, serial ports, printer port, and miscellaneous functions.
The BIOS of a personal computer takes control when power is switched on, setting up the hardware devices, running tests, and booting up the operating system from the disk. (Without a BIOS for the operating system, the machine is an unusable, non-operating collection of hardware components.) The BIOS is a collection of programs stored on a read-only memory chip and is usually considered to be part of the hardware set, but these routines are like any other software. They can be analyzed, understood, modified and re-created as desired, provided that the BIOS resides in programmable media.
Most DOS compatible computers use the same set of bus addresses for addressing similar peripherals and hardware. This enables hardware manufacturers to provide hardware which functions with different computers. The ability to use standardized hardware in a computer has become commonplace.
One type of popular hardware is a memory board residing on an expansion bus (ISA or Industry Standard Architecture bus). The timing problems with buses on DOS compatible computers are varied and complex. Even though the bus address protocols, and often the mechanical dimensions and pin definitions on busses on various DOS compatible computers are reasonably standardized, the exact timing varies among different manufacturers.
The circuits use complementary Metal-Oxide Semiconductor (CMOS) technology. The time delays through any MOS circuit are very dependent on temperature and supply voltage changes. Time variations as great as 50% to 60% over normal temperature-voltage operation are common and 300% from chip to chip variations.
Also, there are several operational modes that further complicate the problem. There are various bus clock speeds from 6 Mhz up to 33 Mhz. There are various wait states: 0, 1 and 2. There are also modes of "normal Row Address Select (RAS)" and "early RAS". Early RAS is composed by decoding the address and other partial results from the bus and applying RAS to the DRAM before the complete bus cycle is present there or starting the DRAM cycle early.
These timing variations have caused many problems for manufacturers of add-on boards for DOS compatible computers.
In the prior art, board manufacturers have dealt with these problems through the careful selection of fixed delays, thus attempting to be compatible with as many DOS compatible computers as possible. These delays are usually controlled by either delay lines or resistor-capacitor circuits.
This invention relates to a timing calibrate and track control (TCTC) circuit which is used to set-up and control critical timing parameters of add-on printed circuit boards plugged into computer buses. The circuit can provide pre-determined timing signals and compensate the signals based on temperature and supply voltage variations.
A first embodiment of the TCTC was designed for use as a memory add-on board for the ISA bus in the IBM AT (T.M.) and other DOS compatible computers. The timing problems associated with the transfer of signals and data within the ISA buses are varied and complex.
As used herein, a bus is a set of signal lines used by an interface system to which a number of devices are connected, and over which information is transferred between devices. There are many manufacturers of DOS compatible computers which share address and pin definitions with the IBM AT. Even though the mechanical dimensions and pin definitions on various AT buses are reasonably standardized, the exact timing varies among different manufacturers. This (TCTC) concept will work for any bus philosophy to speed a bus cycle up.
A popular version of the IBM AT bus had a maximum throughput for memory in input/output (I/O) of about 2.66 megabytes per second. With the use of newer and larger 32-bit processors running at 33 MHz, a condition wherein the signals on the AT bus begin bumping into each other (a phenomenon called "bus ringing") causing the communications on the bus to break down. The potential for spurious signals are increased at these higher frequencies. It can be seen that as personal computers are being used at faster bus cycles, timing becomes more critical.
More specifically, the fetching of data, or instruction cycle, and the writing of data to the DRAM requires time delays for address setup time and hold time, RAS address to RAS delays, and CAS address to CAS delays. This timing is often controlled by a delay circuit using a resistor-capacitor (RC) typically fabricated using complementary metal oxide semiconductor technology. These RC delays are currently fixed by the system hardware and unfortunately are subject to variation as a function of supply voltage and component temperature.
There are several operational modes that further complicate the problem. There are various bus clock speeds from 6 MHz up to 33 MHz and higher. The various clock speeds can complicate the bus timing. The timing is further complicated by the need to accommodate various CPU speeds on a reading of data or instructions in which data has to be present on to the BUS. This means that the CPU speed and data hold times are the complexities that must be dealt with for each board that is instated into the BUS.
There are various wait states typically 0, 1 and 2, that must be dealt with. As the CPU gets faster, each board must analyze how fast the CPU is and when data must be present on the BUS. The appropriate wait states are inserted to match the newly added board with the speed of the CPU. Adding to many wait states slows down the total system; too little wait states as the CPU reads the data and the data is not present, will crash the system.
There are modes of normal Row Address Select (RAS) and early RAS. Decoding the BUS cycle and applying RAS as early as possible into that cycle permits that access to be unique is on the early RAS cycle. Different CPU speeds have different BUS timings and BUS ringing makes the selection somewhat complex for early RAS cycle of the DRAM, however, the normal BUS cycle may require too many wait states therefore, slowing the system down.
These variable timing requirements have caused many problems for manufacturers of add-on boards for AT buses, and the prior art board manufacturers have dealt with these problems through the careful selection of fixed delays, thus attempting to be compatible with as many clones as possible. These delays are usually controlled by either delay lines or resistor-capacitor circuits. It is believed that all board manufacturers use fixed delays and no one is using a method to calibrate and track timing control such as the TCTC.